Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. PLDs typically include an array of configurable logic elements that are programmably interconnected to each other and to programmable input/output blocks via some form of programmable interconnect. This collection of configurable logic may be customized by loading configuration data into internal configuration memory cells that define how the logic elements, interconnect, and input/output blocks are configured.
FIG. 1 is a block diagram depicting one form of PLD 100, which includes configurable logic and interconnect 105, configurable input/output blocks 110, input/output pins 115, and an array of non-volatile memory 120. PLD 100 is customized by loading non-volatile memory 120 with configuration data. PLD 100 then transfers the contents of memory 120 into static random-access memory cells (not shown) within configurable logic and interconnect 105 and input/output blocks 110 when PLD 100 is powered up. In field-programmable gate arrays (FPGAs), one popular form of PLD, non-volatile memory 120 is typically a separate integrated circuit.
FIG. 2 is a six-transistor static random-access memory cell (6T SRAM) 200 employed as in configuration memory of PLD 100 of FIG. 1. SRAM 200 includes a pair of cross-coupled inverters 205 and a pair of first and second access transistors 210A and 210Ab. SRAM 200 additionally includes complementary bitlines BL and BLb connected to the drains of respective access transistors 210A and 210Ab, and a write/read enable terminal WREN connected to the gates of access transistors 210A and 210Ab. Transistors 210A and 210Ab provide access to complementary bit nodes CBIT and CBITb of cross-coupled inverters 205 when an enable signal on write/read enable terminal WREN is asserted.
During a write operation, complementary voltages representative of a specified logic level are presented on complementary bitlines BL and BLb while an enable signal on terminal WREN is asserted. Cross-coupled inverters 205 then retain the complementary voltages, and hence the specified logic level.
During a read operation, an enable signal on terminal WREN connects bit nodes CBIT and CBITb to respective bitlines BL and BLb. Sense amplifiers (not shown) connected to the bitlines then sense the voltage levels provided on the bitlines by bit nodes CBIT and CBITb and provide a corresponding output signal. Inverters 205A and 205B require power to retain a logic level, and so lose stored data when powered down. As a consequence, PLDs that employ memory cell 200 to store configuration data are reconfigured each time power is applied.
The ease with which a given logic function can be implemented using a PLD makes PLDs very economical, especially in smaller quantities. In contrast, application-specific integrated circuits (ASICs) are more expensive for implementing a given design, but may be less expensive to produce in large quantities. Thus, a customer may want to design and implement a logic circuit using a PLD, taking advantage of the ease of design and the attendant reduction in time-to-market. Then, if economies of scale warrant, the customer may want to convert the PLD design into a design specification for a less expensive ASIC, such as a mask-programmed integrated circuit (MPIC).
Some PLD manufacturers offer customers the option of porting a PLD design specification into an ASIC design specification. For example, some manufacturers replace or override internal memory cells with metal connections that similarly define how the logic elements, interconnect, and input/output blocks are configured. The functional circuitry is the same between the original PLD and the mask-programmed ASIC, and this similarity greatly reduces the time and expense associated with porting a PLD design to another form of ASIC. The resulting devices are less expensive than a pure PLD solution because the non-volatile memory portion of the PLD is no longer necessary. For PLD 100 of FIG. 1, the omission of non-volatile memory 120 saves valuable die area, reduces the number of process steps, and improves yield. In FPGAs, the omission eliminates the need for a separate memory IC.
PLDs are complex devices that can be used to instantiate myriad designs. This complexity renders exhaustive testing difficult. Fortunately, generic test procedures that exhaustively test a PLD often obviate the need for design-specific tests: properly specified and simulated PLD designs are assured to work on fully tested PLDs. Unfortunately, when a PLD design is converted to an ASIC design, the resulting ASICs can no longer be tested using generic PLD test procedures. Design-specific tests are therefore developed, at considerable expense, each time a PLD design is ported to an ASIC.